1. Field of the Invention
The present invention relates to a pattern generating apparatus and a pattern shape evaluating apparatus for evaluating the shapes of circuit patterns for electronic devices by use of captured images of the circuit patterns, the circuit patterns being manufactured on a wafer, a reticle or the like.
2. Background Art
In recent years, higher densification and integration of a semiconductor device have been in progress for the purpose of improving the performance of the semiconductor device and reducing the manufacturing costs thereof. Producing semiconductor devices with much higher density and integration requires development of lithography technologies for forming fine circuit patterns on a silicon wafer. The lithography is a process in which a mask is formed as a master pattern for circuit patterns, and in which an exposure apparatus transfers the circuit patterns of the mask onto a photosensitive light-receiving resin (called a resist below) applied on a silicon wafer. The development of the lithography technologies is still in the trend toward finer patterning, thanks to various kinds of technological innovations in the phase shift mask technology, the modified illumination technology, in the scanning exposure technique, in the field of chemically amplified resist materials, and in other related fields.
For a circuit pattern having a minimum size smaller than a wavelength of light from an exposure light source, however, the conventional lithography technologies have a problem of an extreme reduction in a tolerance (hereinafter, called a process window) allowed for each process condition for lithography in the case where the process condition varies from its optimum condition.
There are a wide range of factors of such extreme reduction of the process window, for example, which include: unevenness of illumination accompanying a wavelength shortening of light from an exposure light source; non-uniformity in processes such as antireflection, bake, and development; and variations in mask size. These factors of variations in the lithography processes can be classified into an effective dose (simply called a dose below) that behaves in the same manner as variations in an exposure light amount, and an effective focus (simply called a focus below) that behaves in the same manner as variations in focus.
For this reason, in the course of development of new semiconductor devices, semiconductor manufacturers make an attempt to increase process windows through the following operations. In one of the operations, the process windows for a dose range and a focus range for manufacturing non-defective patterns are figured out by measuring test patterns with use of a length measuring SEM, the test patterns formed on a silicon wafer with the dose and focus being changed stepwisely (hereinafter, this operation is called a condition finding operation. See Japanese Patent Application Publication No. Hei 11-288879). In another one of the operations, optimum conditions for lithography are derived by repeatedly analyzing the factors of dose variations and focus variations through optical simulations.
As for processes on patterns in size of 65 nm or finer, however, the condition finding operation in the course of the development has a difficulty of finding the optimum process windows for all the combinations of pattern shapes and pattern arrangements due to a high density of the patterns and high pattern complexity. Accordingly, more importance is now placed on the monitoring of a deformation of a pattern shape caused by process variations in mass production processes.
An effective method for monitoring a deformation of a pattern shape caused by process variations in mass production processes is a method of obtaining a deformation amount in a pattern shape in a chip by comparing the pattern shape in the chip with the pattern shape of a pattern representing a non-defective pattern whose pattern shape is not deformed at all by the process variations (hereinafter, the pattern is called a reference pattern). As such pattern shape evaluation methods, there have been disclosed the inventions in which a pattern shape is evaluated by using the design data on an electronic device as the reference pattern (Japanese Patent Application No. Hei 7-260699, Japanese Patent Application Publications Nos. Hei 10-312461, 2002-6479 and 2001-338304 (corresponding to U.S. Pat. No. 6,868,175)), and the invention in which a pattern shape is evaluated by using a non-defective pattern as the reference pattern (Japanese Patent Application Publication No. Hei 10-312461).